1. Field of the Invention
The present invention relates generally to a lateral-transistor DRAM memory cell and its manufacturing methods and, more particularly, to a self-aligned lateral-transistor DRAM cell structure and its manufacturing methods.
2. Description of Related Art
A dynamic random-access-memory (DRAM) cell including an access transistor and a storage capacitor has become the most important storage element in electronic system, especially in computer and communication system. The DRAM density is increased very rapidly in order to decrease the cost per bit and, therefore, an advanced photolithography is in general needed to decrease the minimum-feature-size (F) of a cell.
The output voltage of a DRAM cell is proportional to the capacitance value of the storage capacitor of the DRAM cell and, therefore, the storage capacitor must have a satisfactory capacitance value to have stable operation of the cell as the applied voltage is scaled. Basically, the storage capacitor can be implemented in a trench-type or a stack-type. The trench-type is formed by forming a deep trench in a semiconductor substrate without increasing the surface area of the semiconductor-substrate surface. The stack-type is formed by implementing a capacitor structure over the access transistor and its nearby dummy-transistor structure through the conductive contact-plug over the node diffusion region of the access transistor. Basically, the cell size of the stack-type DRAM is limited by a dummy transistor being formed over the isolation region. Accordingly, the limit cell size of the stack-type DRAM is 8 F2 for shallow-trench-isolation. However, the cell size of a trench-type lateral-transistor DRAM is limited by the space between nearby deep-trench capacitors and the separation between the lateral access transistor and the deep-trench capacitor. Therefore, the limit cell size of a trench-type lateral-transistor DRAM is also 8 F2 if the separation between the lateral access transistor and the trench capacitor can""t be minimized.
A typical example of a trench-type lateral-transistor DRAM cell is shown in FIG. 1, in which a deep trench is formed in a semiconductor substrate 100. A trench capacitor is formed in a lower portion of the deep trench, in which a lower capacitor node 101 is formed by a heavily-doped n+ diffusion region using an arsenic-silicate-glass (ASG) film as a dopant diffusion source; an upper capacitor node 103a is made of doped polycrystalline-silicon; and a capacitor-dielectric layer 102 is formed by a composite dielectric layer such as an oxide-nitride-oxide structure or a nitride-oxide structure. An oxide collar 104 is used to separate the lower capacitor node 101 from a source diffusion region 105a, 105b, and a capacitor-node connector 103b being made of doped polycrystalline-silicon is used to electrically connect the upper capacitor node 103a to a source conductive node 103c. The source conductive node 103c is made of heavily-doped polycrystalline-silicon to act as a dopant diffusion source for forming an n+ source diffusion region 105a. A shallow-trench-isolation (STI) region 106 is filled with a CVD-oxide layer in order to separate nearby trench capacitors. Two gate-stacks 108, 109 are formed over an upper surface, in which one gate-stack 108 is acted as a passing word-line and another gate-stack 109 is acted as an excess transistor. A common-source diffusion region 105b, 105a and a common-drain diffusion region 107 for a bit-line node are formed in an upper surface portion of the semiconductor substrate 100. From FIG.1, it is clearly seen that the limit cell size is 8 F2 if the space between two nearby trench capacitors is defined to be a minimum-feature-size (F) of technology used.
Apparently, the common-source diffusion region 105b can be removed and the gate-stack 109 shown in FIG. 1 can be formed in a self-aligned manner, then the semiconductor surface area occupied by a cell can be reduced to be 6 F2.
It is, therefore, a major objective of the present invention to offer a self-aligned lateral-transistor DRAM cell structure for obtaining a cell size of 6 F2 or smaller by using self-aligned techniques.
It is another objective of the present invention to easily offer different implant regions for forming punch-through stops and adjusting threshold-voltages of the lateral transistor and the parasitic collar-oxide transistor in a self-aligned manner so a deeper trench is not required.
It is a further objective of the present invention to offer a manufacturing method for forming a self-aligned lateral-transistor DRAM cell structure and its contactless DRAM arrays with less critical masking photoresist steps.
It is yet another objective of the present invention to offer two different contactless DRAM array structures for high-speed read and write operations.
A self-aligned lateral-transistor DRAM cell structure and its contactless DRAM arrays are disclosed by the present invention. The self-aligned lateral-transistor DRAM cell structure comprises a trench structure and a self-aligned lateral-transistor structure, in which the trench structure comprises a deep-trench region having a trench capacitor and a second-type shallow-trench-isolation region being formed in a side portion of the deep-trench region and the self-aligned lateral-transistor structure comprises a merged common-source diffusion region, a self-aligned gate-stack region, a self-aligned common-drain diffusion region, and different implant regions under the self-aligned lateral-transistor structure for forming punch-through stops of the self-aligned lateral-transistor and the parasitic collar-oxide transistor. The deep-trench region comprises a lower capacitor node made of an n+ diffusion region being formed in a lower portion of a deep trench, a capacitor-dielectric layer being formed over the lower capacitor node, an upper capacitor node being formed over the capacitor-dielectric layer, a collar-oxide layer together with a capacitor-node connector being formed over a portion of the capacitor-dielectric layer and the upper capacitor node, and a source conductive node defined by a first sidewall dielectric spacer being formed over the collar-oxide layer and the capacitor-node connector to act as a dopant diffusion source for forming a merged common-source diffusion region. The second-type shallow-trench-isolation region being formed in a side portion of the deep-trench region comprises a second-type first raised field-oxide layer with a bottom surface level approximately equal to that of the collar-oxide layer and an n+ diffusion region being formed under the second-type first raised field-oxide layer. The self-aligned gate-stack region comprises a highly conductive-gate layer over a gate-dielectric layer being defined by a third sidewall dielectric spacer is formed outside of a second sidewall dielectric spacer. The self-aligned common-drain diffusion region of a second conductivity type comprises a lightly-doped common-drain diffusion region being formed by aligning to the self-aligned gate-stack region and a shallow heavily-doped common-drain diffusion region being formed within the lightly-doped common-drain diffusion region by aligning to a fourth sidewall dielectric spacer being formed over an outer sidewall of the self-aligned gate-stack region. The merged common-source diffusion region of the second conductivity type is formed near the source conductive node under the second sidewall dielectric spacer. The cell size of the self-aligned lateral-transistor DRAM cell structure can be fabricated to be equal to 6 F2 or smaller.
The self-aligned lateral-transistor DRAM cell structure of the present invention is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of self-aligned lateral transistor DRAM cells, a plurality of metal bit-lines integrated with planarized common-drain conductive islands being patterned to be aligned above a plurality of active regions, and a plurality of capping conductive-gate layers over conductive-gate layers to act as a plurality of conductive word-lines being formed transversely to the plurality of metal bit-lines. A second-type contactless DRAM array comprises a plurality of self-aligned lateral-transistor DRAM cells, a plurality of metal word-lines integrated with planarized capping conductive-gate islands over conductive-gate islands being patterned to be aligned above a plurality of active regions, and a plurality of highly conductive common-drain bus-lines acted as a plurality of conductive bit-lines being formed transversely to the plurality of metal word-lines.